Description:
RFIC Design Manager/Director
We are looking for an accomplished and proven Engineering Director to take charge of RF front-end architecture, process technology trade-offs such as BiCMOS vs. CMOS, circuit design, analog/RF layout considerations, testing and characterization of RF ASICs. This person will be responsible for the design and delivery of Ultra Wideband wireless transceiver ASICs which comprise broad-band LNAs, VGAs, very low jitter high frequency clock synthesizers, very high speed ADCs and DACs, high speed serilizers and de-serializers and high speed interface circuits. This leader will advise/work with the system architecture, Baseband, and MAC groups to define, improve, and implement the RF front end for achieving lower power, low BER, long receive range, and high data rate. It will also be this persons responsibility to determine the die size, right packaging and performance trade-offs. He or she will be responsible for the circuit design and layout CAD tools and advise management of the new tools for efficiency and accuracy improvement.
Experience and education:
The prospective candidate should have a MSEE (PhD strongly preferred) in electrical engineering with circuit design emphasis and 12 to 15 years of experience in RFIC design in a semiconductor company environment. This person will need to have at least 5 years experience in the management of successful RFIC design groups. Good understanding of process technologies and device characteristics is essential to successful circuit design. However, proven track record in the design and delivery of wireless RFICs is the paramount consideration, implying dedication to accurate design and layout.
|
